Field
The present invention relates to a drive apparatus that drives a power device such as an IGBT or MOSFET, and a high-voltage level shift circuit used for the drive apparatus.
Background
FIG. 9 is a diagram illustrating a conventional drive circuit. The drive circuit is provided with a high-voltage level shift circuit 100, a transmission circuit 101 and a driver circuit 102. The high-voltage level shift circuit 100 includes resistors R1 and R2, and high withstand voltage field-effect transistors (hereinafter referred to as “HNMOS transistors”) T1 and T2. The transmission circuit 101 includes an RS-type flip flop 103, NOR gates 104 and 105, NAND gates 106 and 107, I/V signal conversion circuit gates 108 and 109, and a mask signal circuit 110 made up of an AND gate. The driver circuit 102 is connected to a power device and drives the power device through its output signal.
A high-potential side signal is inputted to the high-voltage level shift circuit 100 for controlling an on/off operation of the power device. The high-potential side signal is a pulsed signal, inputted to T1 and T2 of the high-voltage level shift circuit 100 and level-shifted to a high potential. The level-shifted on signal or off signal is transmitted from the driver circuit 102 to the power device via the transmission circuit 101.
Generally, a load of a power device driven by a drive circuit is often an inductance load such as a motor. Under influences of a parasitic inductance component due to an inductance load, wiring on a printed wiring board or the like, a high-potential side reference potential VS of the drive circuit at the time of switching fluctuates toward a negative side with respect to a low potential side ground GND. The high-potential side signal becomes an error signal when the high-potential side reference fluctuating toward the negative side is restored to a low potential side reference. Furthermore, this error signal may also be generated by dV/dt when the high-potential side reference potential transitions from a low potential to a high potential.
The error signal causes a current to flow into the level shift resistors R1 and R2 connected to a high-potential side power supply via the parasitic capacitances or parasitic diodes of T1 and T2. This causes a voltage drop and causes the error signal to be transmitted to the transmission circuit 101 at the following stage, which may induce a malfunction of the power device.
As a countermeasure for this malfunction, a logic filter scheme is used in a conventional drive circuit. That is, a mask signal circuit 110 that generates a signal for cancelling an error signal is provided. More specifically, the mask signal circuit 110 generates a mask signal for masking, when both an on signal and an off signal become active, these signals so that they are not transmitted to the RS-type flip flop 103. This mask signal is used to mask main signals outputted from the NAND gates 106 and 107. At this time, although the main signal and the mask signal are set to the same operation region, if a variation occurs in each operation region, an error signal may be transmitted to the transmission circuit 101 at the following stage.
FIG. 10 is a timing chart illustrating operation of a conventional drive circuit. A case is assumed here where an on signal or an off signal, which is an output of the high-voltage level shift circuit 100, abruptly drops under influences of dV/dt or the like and a threshold of the NAND gate 106 or 107 is different from a threshold of the mask signal circuit 110 due to a variation or the like. The threshold of the NAND gate 106 or 107 is shown by a broken line B′ and the threshold of the AND gate of the mask signal circuit 110 is shown by a broken line A′. In this case, a range in which the mask signal is active (high) is narrower than a range in which the main signal becomes inactive (low) due to some trouble. For this reason, the error signal which is the main signal that is erroneously inactivated is not sufficiently masked. Thus, an error signal is generated in a latch input signal which is a set input signal of the RS-type flip flop 103.
In contrast, a level shift circuit that provides a stable operation is disclosed (e.g., see JP 2010-161753 A). However, in addition to an HVNMOS that generates a level shift current, a current is caused to steadily flow into a level shift circuit by another constant current source for stable operation.